The present invention relates to a method for forming an array of dynamic random access memory (DRAM) cells; and, more particularly, to a method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique.
Referring to FIG. 1, there is shown a schematic diagram of a typical dynamic random access memory (DRAM) cell 100 having a field effect transistor (FET) 105 as an access transistor or as a transfer transistor for controlling charge transfer and a storage capacitor Cs for storing charges. The gate of the FET 105 acts as an word line W/L. A bitline B/L is connected to one terminal of the FET 105, the terminal acting as the source or drain of the DRAM cell 100, depending on the application, such as read or write operations.
The other terminal of the FET 105 is connected to a first electrode 110 as a strap or storage node of the storage capacitor Cs. A second electrode 115 as a capacitor plate of the storage capacitor Cs, wherein the second electrode 115 is connected to a predetermined potential such as ground potential. When the FET 105 is turned on by an appropriate signal on the wordline W/L, data is transferred between the bitline B/L and the storage node 110.
High integration density of DRAM cells requires reduction of the area of each of the DRAM cells. While it is desirable to increase the integration density of DRAM cells by rendering an access transistor and a storage capacitor in a DRAM cell smaller, a capacitor therein nonetheless must be large enough to store sufficient charges for ensuring that data is correctly read from and written to the DRAM cell. In this respect, the so-called deep trench capacitors (DTCs) have been developed to increase the capacitance of the storage capacitor while permitting the integration density of the DRAM cell to be increased.
Various techniques have been employed for connecting a DTC to an access transistor in a DRAM cell. For example, a self-aligned buried strap formation technique is known in the art as described in U.S. Pat. No. 5,670,805 issued to Hammerl et al. and U.S. Pat. No. 5,360,758 issued to Bronner et al.
FIG. 2 offers a top plan view illustrating a layout of a conventional array of DRAM cells. FIG. 3 is a cross-sectional view of a DRAM cell 210 taken along a line H-Hxe2x80x2 of FIG. 2. Referring to FIGS. 2 and 3, it could be readily understood that the DRAM cell 210 comprises two deep trench areas (DTAs) DTA1 and DTA2 and one active area (AA). As is well-known in the art, an AA and a DTA represent areas that one or more access transistors and one DTC are to be formed therein, respectively.
In a conventional DRAM cell layout, a DRAM cell is separated from each other by the so-called a field region (FR) or field oxide region (FOR) as shown in FIG. 2. The FR represents an area separating adjacent AAs from each other and/or adjacent DTAs from each other with a relatively thick field oxide that surrounds and electrically isolates each AA and each DTA in and on a substrate.
One of conventional methods for forming FR is the so-called shallow trench isolation (STI) in which trenches are etched in the substrate and filled with a chemical vapor deposited (CVD) oxide that is made planar with the substrate. Referring to FIG. 2, it could be understood that the conventional array of DRAM cells formed by employing such a STI technique includes the so-called island type AAs.
Referring back to FIG. 3, the DRAM cell 210 comprises two DTCs DTC1 and DTC2 formed in deep trenches (DTs) DT1 and DT2, respectively; and two field effect transistors (FETs) FET1 and FET2 formed in a substrate 305 doped with p-type material, e.g., having a p-well 310 formed therein. The DTC1 includes a capacitor plate 315, a collar oxide 375, a storage node 371 and a buried strap 373. The DTC2 includes a capacitor plate 395, a collar oxide 385, a storage node 381, and a buried strap 383.
The FET1 includes N+ source/drain regions 333 and 335, a poly-silicon gate 325 insulatively spaced from the channel between N+ source/drain regions 333 and 335. The FET2 includes N+ source/drain regions 343 and 335, a poly-silicon gate 355 insulatively spaced from the channel between N+ source/drain regions 343 and 335.
Gate contacts 370 and 360 electrically connect the poly-silicon gates 325 and 355 to a word line (not shown), respectively. An insulator 380 covers the gate contact 370 and the poly-silicon gate 325; and an insulator 365 covers the gate contact 360 and the poly-silicon gate 355. A bit line contact 386 electrically connects the N+ source/drain region 335, which is a common source/drain region for both the FET1 and the FET2, to a bit line 390.
A diffusion region 374 is formed as a conductive path to electrically connect the storage node 371 to the N+ source/drain region 333 through the buried strap 373 by outdiffusing dopants from the highly doped poly-silicon fill in the DT1 into the p-well 310. A diffusion region 384 is also formed as a conductive path to electrically connect the storage node 381 to the N+ source/drain region 343 through the buried strap 383 by outdiffusing dopants from the highly doped poly-silicon fill in the DT2 into the p-well 310.
Shallow trench isolation (STI) arrangements 350 and 450, filled with an insulating material, e.g., oxide, isolate the DRAM cell 210 from its adjacent DRAM cells; and isolate the DRAM cell 210 from passing poly-silicon gates 351 and 451.
It should be noted that the conventional array of DRAM cells results in the so-called island type layout as illustrated in FIG. 2 since adjacent storage nodes are isolated during AA formation or STI. In this DRAM cell layout, the overlay between an AA and a corresponding DTA becomes very critical to the device performance, rendering the DRAM cell fabrication process difficult.
Moreover, in the conventional array of DRAM cells, DTCs are fabricated before AA formation to meet the overlay requirements, which, in turn, limits the so-called thermal budget during the STI process. Exceeding this thermal budget leads to an excessive outdiffiision from the trench poly-silicon fill constituting the storage node to underneath the gate and neighboring DRAM cells (374 and 384). This dopant outdiffusion may result in unacceptable changes of the characteristics of the access transistor as well as electrical leakage between neighboring DRAM cells.
In addition, as is well-known in the art, the limitation on the thermal budget after buried strap formation limits the following oxidation steps and conflicts with the need for thermal anneals to heal implantation damage or to relieve stress built up in the substrate, e.g., a silicon substrate, during the DRAM cell fabrication process.
Conventional techniques such as those described in the above-mentioned U.S. Pat. Nos. 5,670,805 and 5,360,758 have been suggested to relieve the thermal budget problem. But none the conventional techniques including these techniques are sufficient enough to solve the thermal budget problem since they have the basic limitation that DTCs are fabricated before AA patterning.
Further, the lithography of the island type pattern of the conventional array of DRAM cell can be problematic or difficult, especially on a non-uniform topological region, e.g., on top of a DT.
It is, therefore, an object of the present invention is to provide a method for forming an array of DRAM cells by patterning line type active areas (AAs), thereby rendering patterning of the AAs easier.
Another object of the present invention is to provide a method for forming an array of DRAM cells by employing a maskless self-aligned adjacent node isolation technique to thereby eliminate the issue of the overlay or improve the overlay margin between an AA and a corresponding DTA in a DRAM cell.
A further object of the present invention is to provide a method for forming an array of DRAM cells by forming line type AAs before DTCs are formed to thereby solve the thermal budget problem.
In order to achieve the above-mentioned objects of the present invention, there is provided a method for forming an array of dynamic random access memory (DRAM) cells, comprising the steps of: (a) patterning line type active areas (AAs) on a substrate to thereby provide AA lines (AALs); (b) fabricating deep trench capacitors (DTCs) in each of the AALs in a predetermined configuration, thereby defining deep trench areas (DTAs) for the DTCs; and (c) defining a node isolation area (NIA) to isolate storage nodes of two adjacent DTCs and then defining a trench insulation area (TIA) for each of the DRAM cells. The order of (a) and (b) can be interchanged as it will be described in detail to have an advantage of thermal budget.